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precision, high speed, bifet quad op amp ad713 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2002C2011 analog devices, inc. all rights reserved. features ac performance 1 s settling to 0.01% for 10 v step 20 v/s slew rate 0.0003% total harmonic distortion (thd) 4 mhz unity gain bandwidth dc performance 1.5 mv maximum offset voltage 8 v/c maximum drift 150 v/mv minimum open-loop gain 2 v p-p typical noise, 0.1 hz to 10 hz true 14-bit accuracy single version: ad711, dual version: ad712 available in 16-lead soic, 14-lead pdip and cerdip applications active filters quad output buffers for 12- and 14-bit dacs input buffers for precision adcs photo diode preamplifier applications connection diagrams 00824-001 ad713 top view (not to scale) 1 2 3 4 output 14 ?in 13 +in 12 ?v s 11 5 +in 10 6 ?in 9 7 output o utput ?in +in +v s +in ?in o utput 8 4 1 3 2 figure 1. 14-lead pdip (n) and cerdip (q) packages 00824-002 nc = no connect. do not connect to this pin. output 1 ?in 2 +in 3 +v s 4 output 16 ?in 15 +in 14 ?v s 13 +in 5 +in 12 ?in 6 ?in 11 output 7 output 10 nc 8 nc 9 4 1 3 2 ad713 top view (not to scale) figure 2. 16-lead soic_w (rw) package general description the ad713 is a quad operational amplifier, consisting of four ad711 bifet op amps. these precision monolithic op amps offer excellent dc characteristics plus rapid settling times, high slew rates, and ample bandwidths. in addition, the ad713 provides the close matching ac and dc characteristics inherent to amplifiers sharing the same monolithic die. the single-pole response of the ad713 provides fast settling: l s to 0.01%. this feature, combined with its high dc precision, makes the ad713 suitable for use as a buffer amplifier for 12- or 14-bit dacs and adcs. it is also an excellent choice for use in active filters in 12-, 14- and 16-bit data acquisition systems. furthermore, the ad713 low total harmonic distortion (thd) level of 0.0003% and very close matching ac characteristics make it an ideal amplifier for many demanding audio applications. the ad713 is internally compensated for stable operation at unity gain. the ad713j is rated over the commercial temperature range of 0c to 70c. the ad713a is rated over the industrial temperature of ?40c to +85c. the ad713 is offered in 16-lead soic, 14-lead pdip, and 14-lead cerdip packages. product highlights 1. the ad713 is a high speed bifet op amp that offers excellent performance at competitive prices. it upgrades the performance of circuits using op amps such as the tl074, tl084, lt1058, lf347, and opa404. 2. slew rate is 100% tested for a guaranteed minimum of 16 v/s (j and a grades). 3. the combination of analog devices, inc., advanced processing technology, laser wafer drift trimming, and well-matched ion-implanted jfets provides outstanding dc precision. input offset voltage, input bias current and input offset current are specified in the warmed-up condition and are 100% tested. 4. very close matching of ac characteristics between the four amplifiers makes the ad713 ideal for high quality active filter applications.
ad713 rev. d | page 2 of 20 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? connection diagrams...................................................................... 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? absolute maximum ratings............................................................ 5 ? thermal resistance ...................................................................... 5 ? esd caution.................................................................................. 5 ? typical performance characteristics ............................................. 6 ? test circuits..................................................................................... 10 ? theory of operation ...................................................................... 11 ? measuring ad713 settling time ............................................. 11 ? power supply bypassing ............................................................ 11 ? a high speed instrumentation amplifier circuit................. 12 ? a high speed 4-op-amp cascaded amplifier circuit ........ 12 ? high speed op amp applications and techniques .............. 12 ? cmos dac applications ......................................................... 14 ? filter applications ...................................................................... 14 ? gic and fdnr filter applications ......................................... 15 ? outline dimensions ....................................................................... 17 ? ordering guide .......................................................................... 18 ? revision history 5/11rev. c to rev. d updated format..................................................................universal changes to features section, general description section, and product highlights section ............................................................. 1 deleted s, k, b, and t grades throughout................................... 1 changes to table 1............................................................................ 3 changes to table 2............................................................................ 5 added typical performance characteristics summary .............. 6 change to figure 7 ........................................................................... 7 changes to figure 15, figure 17, and figure 18 ........................... 8 deleted figure 9 and figure 10; renumbered sequentially........ 9 changes to figure 23 caption and figure 24 caption .............. 10 added test circuits section .......................................................... 11 moved figures 26, figure 27, and figure 28 ............................... 11 changes to figure 29...................................................................... 12 changes to dac buffers (i-to-v converters) section.............. 13 changes to figure 37 and table 5................................................. 14 changed c1 to c l ........................................................................... 14 changes to figure 43 and figure 44............................................. 15 updated outline dimensions....................................................... 18 changes to ordering guide .......................................................... 19 10/01rev. b to rev. c edits to features.................................................................................1 edits to product description ...........................................................1 edits to ordering guide ...................................................................3 edits to metallization photograph ..................................................3
ad713 rev. d | page 3 of 20 specifications v s = 15 v at t a = 25c, unless otherwise noted. table 1. ad713j/ad713a parameter test conditions/comments min typ max unit input offset voltage 1 initial offset 0.3 1.5 mv offset t min to t max 0.5 2 mv vs. temp 5 v/c vs. supply 78 95 db t min to t max 76 95 db long-term stability 15 v/month input bias current 2 v cm = 0 v 40 150 pa v cm = 0 v at t max 3.4/9.6 na v cm = 10 v 55 200 pa input offset current v cm = 0 v 10 75 pa v cm = 0 v at t max 1.7/4.8 pa matching characteristics input offset voltage 0.5 1.8 mv t min to t max 0.7 2.3 mv input offset voltage drift 8 v/c input bias current 10 100 pa crosstalk f = 1 khz ?130 db f = 100 khz ?95 db frequency response small signal bandwidth g = ?1 3.0 4.0 mhz full power response v o = 20 v p-p 200 khz slew rate g = ?1 16 20 v/s settling time to 0.01% 1.0 1.2 s total harmonic distortion f = 1 khz; r l 2 k; v o = 3 v rms 0.0003 % input impedance differential 3 3 10 12 ||5.5 ||pf common mode 4 3 10 12 ||5.5 ||pf input voltage range differential 20 v common-mode voltage +14.5/?11.5 v t min to t max ?11 +13 v common mode v cm = 10 v 78 88 db rejection ratio t min to t max 76 84 db v cm = 11 v 72 84 db t min to t max 70 80 db input voltage noise 0.1 hz to 10 hz 2 v p-p f = 10 hz 45 nv/hz f = 100 hz 22 nv/hz f = 1 khz 18 nv/hz f = 10 khz 16 nv/hz input current noise f = 1 khz 0.01 pa/hz open-loop gain v o = 10 v; r l 2 k 150 400 v/mv t min to t max 100 v/mv
ad713 rev. d | page 4 of 20 ad713j/ad713a parameter test conditions/comments min typ max unit output characteristics voltage r l 2 k +13/?12.5 +13.9/?13.3 v t min to t max 12 +13.8/?13.1 v current short circuit 25 ma power supply rated performance 15 v operating range 4.5 18 v quiescent current 10.0 13.5 ma transistor count number of transistors 120 1 input offset voltage specifications are gua ranteed after 5 minutes of operation at t a = 25c. 2 bias current specifications are guaranteed maximum at either input after 5 minutes of operation at t a = 25c. for higher temperatures, the current doubles every 10c. 3 defined as the voltage between inputs, such that neither exceeds 10 v from ground. 4 typically exceeding ?14.1 v negative common-mode voltage on either input results in an output phase reversal.
ad713 rev. d | page 5 of 20 absolute maximum ratings table 2. parameter rating supply voltage 18 v input voltage 1 18 v output short-circuit duration (for one amplifier) indefinite differential input voltage +v s and ?v s storage temperature range (q) ?65c to +150c storage temperature range (n, r) ?65c to +125c operating temperature range ad713j 0c to 70c ad713a ?40c to +85c lead temperature range (soldering, 60 sec) 300c 1 for supply voltages less than 18 v, the absolute maximum input voltage is equal to the supply voltage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja jc unit 14-lead pdip (n-14) 100 30 c/w 14-lead cerdip (q-14) 110 30 c/w 16-lead soic_w (rw-16) 100 30 c/w esd caution
ad713 rev. d | page 6 of 20 typical performance characteristics v s = 15 v at t a = 25c, unless otherwise noted. 20 15 10 5 0 0 5 10 15 20 supply voltage (v) input voltage swing (v) 00824-003 r l = 2k ? t a = 25c figure 3. input voltage swing vs. supply voltage 20 15 +v out ?v out 10 5 0 0 5 10 15 20 supply voltage (v) output voltage swing (v) 00824-004 r l = 2k ? t a = 25c figure 4. output voltage swing vs. supply voltage 30 25 20 15 10 5 0 10 100 1k 10k load resistance ( ? ) output voltage swing (v p-p) 00824-005 15v supplies figure 5. output voltage swing vs. load resistance 16 12 8 4 0 0 5 10 15 20 supply voltage (v) quiescent current (ma) 00824-006 figure 6. quiescent current vs. supply voltage 10 ?6 10 ?7 10 ?8 10 ?9 10 ?10 10 ?11 10 ?12 ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) input bias current (a) 00824-007 figure 7. input bias current vs. temperature 100 10 1 0.1 0.01 1k 10k 100k 1m 10m frequency (hz) output impedance ( ? ) 00824-008 figure 8. output impeda nce vs. frequency, g = 1
ad713 rev. d | page 7 of 20 50 40 v s = 15v t a = 25c 30 20 10 0 ?10 ?5 0 5 10 common-mode voltage (v) input bias current (pa) 00824-009 figure 9. input bias current vs. common mode voltage 26 24 22 20 18 16 14 12 10 ?60 0 ?20?40 40 20 60 80 100 120 140 ambient temperature (c) short circuit current limit (ma) 00824-010 +output current ?output current figure 10. short-circuit cu rrent limit vs. temperature 5.0 4.5 4.0 3.5 3.0 ?60 0 ?20?40 40 20 60 80 100 120 140 temperature (c) unity gain bandwidth (mhz) 00824-011 figure 11. gain bandwidth vs. temperature 100 80 60 40 20 0 ?20 80 100 60 40 20 0 ?20 10 100 10k 1k 100k 1m 10m frequency (hz) open-loop gain (db) phase margin (degrees) 00824-012 gain phase 2k ? ||100pf load figure 12. open-loop gain and phase margin vs. frequency 125 120 115 110 105 100 95 0 5 10 15 20 supply voltage (v) open-loop gain (db) 00824-013 r l = 2k ? t a = 25c figure 13. open-loop gain vs. supply voltage 110 100 80 60 40 20 0 10 100 1k 10k 100k 1m supply modulation frequency (hz) power supply rejection (db) 00824-014 v s = 15v supplies with 1v p-p sine wave 25c +supply ?supply figure 14. power supply rejection vs. frequency
ad713 rev. d | page 8 of 20 100 80 60 40 20 0 10 100 1k 10k 100k 1m frequency (hz) cmr (db) 00824-015 v s = 15v v cm = 1v p-p t a = 25c figure 15. common-mode rejection vs. frequency 30 25 20 15 10 5 0 100k 10m 1m input frequency (hz) output voltage (v p-p) 00824-016 r l = 2k ? t a = 25c v s = 15v figure 16. large signal frequency response 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 0.5 1.0 0.7 0.8 0.9 0.6 settling time (s) output swing from 0v to final volts 00824-017 error 0.1% 1% 0.1% 0.01% 1% 0.01% figure 17. output swing and error vs. settling time 70 80 90 100 110 120 130 100 1k 10k 100k frequency (hz) thd (db) 00824-018 3v rms r l = 2k ? c l = 100pf figure 18. total harmonic distortion vs. frequency 1k 100 10 1 1 10 100 1k 10k 100k frequency (hz) input noise voltage (nv/ hz) 00824-019 figure 19. input noise voltage spectral density 25 20 15 10 5 0 03 0 0 200 100 500 400 600 700 800 900 input error signal (mv) (at summing junction) slew rate (v/s) 00824-020 figure 20. slew rate vs. input error signal
ad713 rev. d | page 9 of 20 ? 70 ?80 ?90 1 to 4 1 to 2 1 to 3 ?100 ?110 ?120 ?130 ?140 10 100 1k 10k 100k frequency (hz) crosstalk (db) 00824-022 1 2 3 4 14 13 12 11 5 10 6 9 7 8 1 2 4 3 figure 21. crosstalk vs. frequency (see figure 26 for test circuit) 00824-024 ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? 100 90 10 0% 5v 1s figure 22. unity gain follower pulse responselarge signal (see figure 27 for test circuit) 00824-026 ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? 100 90 10 0% 50mv 100ns figure 23. unity gain follower pulse responsesmall signal (see figure 27 ) 00824-027 ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? 100 90 10 0% 5v 1s figure 24. unity gain inverter pulse responsesmall signal (see figure 28 ) 00824-028 ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? 100 90 10 0% 50mv 200ns figure 25. unity gain inverter pulse responsesmall signal (see figure 28 )
ad713 rev. d | page 10 of 20 test circuits 00824-021 + 1f 0.1f + 1f 0.1f +v s com ?v s 1/4 ad713 9k? 1k? output all 4 amplifiers are connected as shown. input signal or ground* 1k? ad713 pin 4 ad713 pin 11 * the signal input (1khz sinewave, 2v p-p) is applied to one amplifier at a time. the outputs of the other three amplifiers are then measured for crosstalk. 00824-023 +v s v out v in ?v s 1/4 ad713 4 11 + 1f 0.1f + 1f 0.1f s quare wave input r l 2k ? c l 10pf figure 26. crosstalk test circuit for figure 21 figure 27. unity gain follower circuit for figure 22 and figure 23 00824-025 +v s 2k ? 2k ? v out v in ?v s 1/4 ad713 4 11 + 1f 0.1f + 1f 7.5pf 0.1f square wave input r l 2k ? c l 10pf figure 28. unity gain inverter circuit for figure 24 , and figure 25
ad713 rev. d | page 11 of 20 theory of operation measuring ad713 settling time the error signal is thus clamped twice: once to prevent overload- ing amplifier a2 and then a second time to avoid overloading the oscilloscope preamp. a tektronix oscilloscope preamp type 7a26 was carefully chosen because it recovers from the approximately 0.4 v overload quickly enough to allow accurate measurement of the ad713 1 s settling time. amplifier a2 is a very high speed fet input op amp; it provides a voltage gain of 10, amplifying the error signal output of the ad713 under test (providing an overall gain of 5). figure 30 and figure 31 show the dynamic response of the ad713 while operating in the settling time test circuit of figure 29 . the input of the settling time fixture is driven by a flat-top pulse generator. the error signal output from the false summing node of a1, the ad713 under test, is clamped, amplified by op amp a2, and then clamped again. 00824-029 10k ? 200 ? 4.99k ? 10k ? 4.99k ? 5pf to 18pf +v s ?v s v in + + 10pf 0.1f 0.1f 1f 1f 5k ? 1/4 ad713 a1 4 11 + a2 5pf + 0.2pf to 0.8pf 10k ? 206 ? 2 hp2835 2 hp2835 1.1k ? +v s ?v s 0.47f 0.47f v error 5 * flat-top pulse generator data dynamics 5109 or equivalent * use very short cable or termination resistor notes 1. use circuit board with ground plane. to tektronix 7a26 oscilloscope preamp input section (via less than 1ft 50 ? coaxial cable) 20pf 1m ? 00824-031 ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? 100 90 10 0% 5mv 5v 500ns figure 31. settling characteristics to C10 v step, upper trace: output of ad71 3 under test (5 v/div), lower trace: amplified error voltage (0.01%/div) power supply bypassing the power supply connections to the ad713 must maintain a low impedance to ground over a bandwidth of 4 mhz or more. this is especially important when driving a significant resistive or capacitive load because all current delivered to the load comes from the power supplies. multiple high quality bypass capacitors are recommended for each power supply line in any critical application. as shown in figure 32 , a 0.1 f ceramic and a 1 f electrolytic capacitor placed as close as possible to the amplifier (with short lead lengths to power supply common) assures adequate high frequency bypassing in most applications. a minimum bypass capacitance of 0.1 f should be used for any application. figure 29. settling time test circuit 00824-030 ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? 100 90 10 0% 5mv 5v 500ns 00824-032 + v s ?v s 1/4 ad713 4 11 + 1f 0.1f + 1f 0.1f figure 32. recommended power supply bypassing figure 30. settling characteristics 0 v to 10 v step, upper trace: output of ad71 3 under test (5 v/div), lower trace: amplified error voltage (0.01%/div)
ad713 rev. d | page 12 of 20 a high speed instrumentation amplifier circuit the instrumentation amplifier circuit shown in figure 33 can provide a range of gains from unity up to 1000 and higher using only a single ad713. the circuit bandwidth is 1.2 mhz at a gain of 1 and 250 khz at a gain of 10; settling time for the entire circuit is less than 5 s to within 0.01% for a 10 v step, (g = 10). other uses for amplifier a4 include an active data guard and an active sense input. 10k ? +in ?in sense to buffered voltage reference or remote ground sense 10k ? ** 10k? ** 10k ? ** r g 7.5pf *1.5pf to 20pf (trim for best settling time) 5pf a1 1 3 2 a3 8 9 10 a4 14 13 12 a2 7 6 5 7.5pf 10k ? 10k? ** 1/4 ad713 1/4 ad713 1/4 ad713 1/4 ad713 circuit gain = + 1 20,000 r g voltronics sp20 trimmer capacitor or equivalent ratio matched 1% metal film resistors * ** + 1f 0.1f + 1f 0.1f +v s com ?v s ad713 pin 4 ad713 pin 11 00824-033 figure 33. high speed instrumentation amplifier circuit table 4 provides a performance summary for this circuit. figure 34 shows the pulse response of this circuit for a gain of 10. table 4. performance summary for the high speed instrumentation amplifier circuit gain r g bandwidth settling time (0.01%) 1 nc 1 1.2 mhz 2 s 2 20 k 1.0 mhz 2 s 10 4.04 k 0.25 mhz 2 s 1 nc = no connect. 00824-034 ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? 100 90 10 0% 5v 2s figure 34. pulse response of high speed instrumentation amplifier, gain = 10 a high speed 4-op-amp cascaded amplifier circuit figure 35 shows how the four amplifiers of the ad713 can be connected in cascade to form a high gain, high bandwidth amplifier. this gain of 100 amplifier has a ?3 db bandwidth greater than 600 khz. 1/4 ad713 ?v s + v s 2.15k ? input + 1f 0.1f 1f 0.1f output 4-op-amp cascaded amplifier gain = 100 bandwidth (?3db) = 632khz 1/4 ad713 1k ? 1k ? 1k ? 1k ? 1/4 ad713 2.15k ? 1/4 ad713 2.15k ? 2.15k ? optional v os adjustment +v s ?v s 22m ? 100k ? 00824-035 3 4 1 2 12 11 14 13 5 7 6 10 8 9 figure 35. high speed 4-op-amp cascaded amplifier circuit 00824-036 +v s 10k ? 100k ? 1k ? low distortion sinewave input error signal output (error/11) 1k ? null adjust 10k ? ?v s 1/4 ad713 4 11 + 1f 0.1f + 1f 100pf 0.1f to spectrum analyze r figure 36. thd test circuit high speed op amp applications and techniques dac buffers (i-to-v converters) the wide input dynamic range of jfet amplifiers makes them ideal for use in both waveform reconstruction and digital audio dac applications. the ad713, in conjunction with a 16-bit dac, can achieve 0.0016% thd without requiring the use of a deglitcher in digital audio applications. driving the analog input of an analog-to-digital converter an op amp driving the analog input of an analog-to-digital converter (adc), such as that shown in figure 37 , must be capable of maintaining a constant output voltage under dynami- cally changing load conditions. in successive approximation converters, the input current is compared to a series of switched trial currents. the comparison point is diode clamped but may vary by several hundred millivolts, resulting in high frequency modulation of the analog-to-digital input current. the output impedance of a feedback amplifier is made artificially low by its
ad713 rev. d | page 13 of 20 loop gain. at high frequencies, where the loop gain is low, the amplifier output impedance can approach its open-loop value. sts 1 (msb) db11 high bits middle bits low bits (lsb) db0 2 db10 3 db9 4 28 27 a o 26 25 db8 5 db7 6 db6 7 ce 24 ref out 23 ac 22 db5 8 ref in 21 db4 9 v ee 20 db3 10 bip off 19 db2 11 10v in 18 db1 12 v logic 17 13 v cc 16 dc 14 20v in 15 ad574a top view (not to scale) 12/8 cs r/c gain adjust 10v analog input r2 100 ? r1 100 ? offset adjust analog com 00824-039 1/4 ad713 +15v 0.1f 4 ?15v 0.1f 11 figure 37. ad713 as an adc buffer most ic amplifiers exhibit a minimum open-loop output imped- ance of 25 , due to current limiting resistors. a few hundred microamps reflected from the change in converter loading can introduce errors in instantaneous input voltage. if the analog- to-digital conversion speed is not excessive and the bandwidth of the amplifier is sufficient, the amplifier output returns to the nominal value before the converter makes its comparison. however, many amplifiers have relatively narrow bandwidths, yielding slow recovery from output transients. the ad713 is ideally suited as a driver for adcs because it offers both a wide bandwidth and a high open-loop gain. 00824-040 ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? 100 90 10 0% 1mv ad713 buff 200ns 500mv 10v adc in figure 38. buffer recovery time source current = 2 ma 00824-041 ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? 100 90 10 0% 1mv ad713 buff 200ns 500mv ?5v adc in figure 39. buffer recovery time sink current = 1 ma driving a large capacitive load the circuit of figure 40 uses a 100 isolation resistor that enables the amplifier to drive capacitive loads exceeding 1500 pf; the resistor effectively isolates the high frequency feedback from the load and stabilizes the circuit. low frequency feedback is returned to the amplifier summing junction via the low-pass filter formed by the 100 series resistor and the load capacitance, c l . figure 41 shows a typical transient response for this connection. +v s ?v s 1/4 ad713 4 11 0.1f 30pf 4.99k ? 4.99k ? c l r l 100 ? 0.1f output input typical capacitance limit for various load resistors r l 2k? 10k ? 20k ? c l up to 1500pf 1500pf 1000pf 00824-042 figure 40. circuit for driving a large capacitance load 00824-043 ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? 100 90 10 0% 5v 1s figure 41. transient response, r l = 2 k, c l = 500 pf
ad713 rev. d | page 14 of 20 00824-044 19 out1 agnd 3 dgnd 20 18 v ref ad7545 r1* *refer to table 5. r2* db11 to db0 gain adjust c1 33pf v dd v in v out v dd r fb analog common +15v ?15v 0.1f 0.1f 1/4 ad713 4 11 1 2 cmos dac applications the ad713 is an excellent output amplifier for cmos dacs. it can be used to perform both two- and four-quadrant operation. the output impedance of a dac using an inverted r-2r ladder approaches r for codes containing many 1s, 3r for codes containing a single 1, and infinity for codes containing all 0s. for example, the output resistance of the ad7545 modulates between 11 k and 33 k. therefore, with the dacs internal feedback resistance of 11 k, the noise gain varies from 2 to 4/3. this changing noise gain modulates the effect of the input offset voltage of the amplifier, resulting in nonlinear dac amplifier performance. the ad713, with its guaranteed 1.5 mv input offset voltage, minimizes this effect, achieving 12-bit performance. figure 42. unipolar binary operation filter applications a programmable state variable filter for the state variable or universal filter configuration of figure 44 to function properly, dac a1 and dac b1 must control the gain and q of the filter characteristic, and dac a2 and dac b2 must accurately track for the simple expression of f c to be true. this is readily accomplished using two ad7528 dacs and one ad713 quad op amp. capacitor c3 compensates for the effects of op amp gain bandwidth limitations. figure 42 and figure 43 show the ad713 and a 12-bit cmos dac, the ad7545 , configured for either a unipolar binary (two- quadrant multiplication) or bipolar (four-quadrant multiplication) operation. capacitor c1 provides phase compensation, which reduces overshoot and ringing. table 5. recommended trim resi stor values vs. grades for ad7545 for v d = 5 v this filter provides low-pass, high-pass, and band-pass outputs and is ideally suited for applications where microprocessor control of filter parameters is required. the programmable range for component values shown is f c = 0 khz to 15 khz and q = 0.3 to 4.5. trim resistor jn/aq kn/bq ln/cq gln/gcq r1 500 200 100 20 r2 150 68 33 6.8 1/4 ad713 1/4 ad713 00824-045 19 out1 agnd 20 18 v ref ad7545 r1* r2* r4 20k? 1% r3 10k ? 1% r5 20k ? 1% 12 3 dgnd c1 33pf v dd v in v out v dd r fb analog common 1 2 +15v 0.1f 4 ?15v 0.1f 11 gain adjust data input db11 to db0 *refer to table 5. figure 43. bipolar operation
ad713 rev. d | page 15 of 20 1/4 ad713 a1 +v s v in r3 10k ? r4 30k ? c1 1000pf c3 33pf high pass output r5 30k ? + 1f 4 2 3 1 1/4 ad713 a2 6 5 7 1/4 ad713 a3 9 10 8 ad7528 v dd dac b1 r f 18 19 20 2 1 5 6 16 15 17 14 7 db0 to db7 data 1 dac a/ dacb wr cs dac a1 r s ad7528 v dd 20 18 2 1 5 6 16 15 17 14 7 db0 to db7 data 2 dac a/ dac b wr cs dac a2 r1 4 4 c2 1000pf 1/4 ad713 a4 13 12 14 dac b2 r2 ?v s band pass output low pass output 1f 11 + circuit equations c 1 = c 2 , r 1 = r 2 , r 4 = r 5 f c = 1 2 r 1 c 1 a o = ? r f r s 256 (dac ladder resistance) dac digital code dac equivalent resistance equals q = r 3 r 4 r f r fbb1 00824-046 figure 44. a programmable state variable filter circuit gic and fdnr filter applications the closely matched and uniform ac characteristics of the ad713 make it ideal for use in genera lized impedance converter (gic)/ gyrator and frequency dependent negative resistor (fdnr) filter applications. figure 47 and figure 48 show the ad713 used in two typical active filters. the first shows a single ad713 simulating two coupled inductors configured as a one-third octave band-pass filter. a single section of this filter meets ansi class ii specifications and handles a 7.07 v rms signal with <0.002% thd (20 hz to 20 khz). figure 48 shows a seven-pole antialiasing filter for a 2 over- sampling (88.2 khz) digital audio application. this filter has <0.05 db pass-band ripple and 19.8 s 0.3 s delay, at dc to 20 khz, and handles a 5 v rms signal (v s = 15 v) with no overload at any internal nodes. the filter of figure 47 can be scaled for any center frequency by using the following formula: r c f c 2 11.1 = where all resistors and capacitors scale equally. resistors r3 to r8 should not be greater than 2 k in value to prevent parasitic oscillations caused by the amplifiers input capacitance. if this is not practical, add small lead capacitances (10 pf to 20 pf) across r5 and r6. figure 45 and figure 46 show the output amplitude vs. frequency of these filters. 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 0 102030405060708090100 frequency (mhz) output amplitude (dbm) 00824-048 output amplitude (dbm) 0 ?1 ?2 ?3 ?4 ?5 16 18 20 frequency (mhz) 22 24 figure 45. output amplitude vs. frequency of 1/3 octave filter 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 10k 100k 1m frequency (mhz) relative output amplitude (db) 00824-049 3 2 1 0 ?1 200 500 1k 2k s db 5k 10k 20k 200 500 1k 2k 5k 10k 20k 18 19 20 21 22 output amplitude group delay figure 46. relative output amplitude vs. frequency of antialiasing filter
ad713 rev. d | page 16 of 20 5 6 7 1/4 ad713 2 3 1 1/4 ad713 r3 1300 ? r1 6.19k ? r5 1300 ? r7 1300 ? r9 1300 ? c3 6800pf 12 13 14 1/4 ad713 9 10 8 1/4 ad713 r4 1300 ? r6 1300 ? r2 6.19k ? r8 1300 ? r10 1300 ? r11 5.62k ? c4 6800pf output input c2 6800pf c2 6800pf + 1f 0.1f + 1f 0.1f +v s com ?v s ad713 pin 4 ad713 pin 11 c 1 = c 2 = c 3 = c 4 = c r 3 = r 4 = r 5 = r 6 = r 7 = r 8 = r 9 = r 10 = r r 1 = r 2 = 4.76 ? r 11 = 4.32 ? f c = 1.11 2 rc 00824-047 figure 47. a 1/3 octave filter circuit 00824-050 input 2 3 1 1/4 ad713 a1 10k ? 412 ? 1.74k ? 1.74k ? 330 ? 100k ? 4700pf output 95.3k ? 4700pf + 1f 0.1f + 1f 0.1f +v s com ?v s ad713 pin 4 ad713 pin 11 1k ? 1k ? 36 ? 1.2k ? 4700pf 4700pf 1k ? 1k ? 6 5 7 1/4 ad713 a2 10 9 8 a3 1/4 ad713 1k? 1k? 120 ? 1.87k ? 4700pf 4700pf 13 12 14 1/4 ad713 a4 3 2 1 b1 1/4 ad713 1k ? 1k ? 130 ? 1.1k ? 4700pf 4700pf 6 5 7 1/4 ad713 b2 10 9 8 b3 1/4 ad713 12 13 14 b4 1/4 ad713 figure 48. an antialiasing filter
ad713 rev. d | page 17 of 20 outline dimensions compliant to jedec standards ms-001 controlling dimensions are in inches; millimeter dimensions (in parentheses) are ro unded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. 070606-a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.070 (1.78) 0.050 (1.27) 0.045 (1.14) 14 1 7 8 0.100 (2.54) bsc 0.775 (19.69) 0.750 (19.05) 0.735 (18.67) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.210 (5.33) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) figure 49. 14-lead plastic dual in-line package [pdip] narrow body (n-14) dimensions shown in inches and (millimeters) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 0.310 (7.87) 0.220 (5.59) 0.005 (0.13) min 0.098 (2.49) max 0.100 (2.54) bsc 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 0.785 (19.94) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) pin 1 1 7 8 14 figure 50. 14-lead ceramic dual in-line package [cerdip] (q-14) dimensions shown in inches and (millimeters)
ad713 rev. d | page 18 of 20 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013-aa 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) c oplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc 03-27-2007-b figure 51. 16-lead standard small outline package [soic_w] wide body (rw-16) dimensions shown in millimeters and (inches) ordering guide model 1 temperature range package description package option ad713aq ?40c to +85c 14-lead cerdip q-14 ad713jnz 0c to 70c 14-lead pdip n-14 ad713jr-16 0c to 70c 16-lead soic_w rw-16 ad713jr-16-reel 0c to 70c 16-lead soic_w rw-16 ad713jr-16-reel7 0c to 70c 16-lead soic_w rw-16 AD713JRZ-16 0c to 70c 16-lead soic_w rw-16 AD713JRZ-16-reel 0c to 70c 16-lead soic_w rw-16 AD713JRZ-16-reel7 0c to 70c 16-lead soic_w rw-16 1 z = rohs compliant part.
ad713 rev. d | page 19 of 20 notes
ad713 rev. d | page 20 of 20 notes ?2002C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00824-0-5/11(d) ?2002C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00824-0-5/11(d)

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